module adder(a, b, sel, out, carry, overflow, zero);
  input [3:0] a;
  input [3:0] b;
  input sel;
  output [3:0] out;
  output carry;
  output overflow;
  output zero;

  wire [3:0] b_add_sel;

  assign b_add_sel = ({4{sel}} ^ b) + {3'b000, sel};
  assign {carry, out} = a + b_add_sel;
  assign overflow = (a[3] == b_add_sel[3]) && (out[3] != a[3]);

  assign zero = ~(| out);

endmodule

